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1. general description the UDA1384 is a single-chip consisting of 4 plus 1 analog-to-digital converters (adc) and 6 digital-to-analog converters (dac) with signal processing features employing bitstream conversion techniques. the multichannel con?guration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature. the UDA1384 supports conventional 2 channels per line data transfer conformable to the i 2 s-bus format with word lengths of up to 24 bits, the msb-justi?ed format with word lengths of up to 24 bits and the lsb-justi?ed format with word lengths of 16 bits, 20 bits and 24 bits, as well as 4 channels to 6 channels per line transfer mode. the device also supports a combination of the msb-justi?ed output format and the lsb-justi?ed input format. the UDA1384 has special sound processing features in the direct stream digital (dsd) playback mode, de-emphasis, volume and mute which can be controlled via the l3-bus or i 2 c-bus interface. 2. features 2.1 general n 2.7 v to 3.6 v power supply n 5 v tolerant digital inputs n 24-bit data path n selectable control: via l3-bus or i 2 c-bus microcontroller interface n supports sample frequency ranges for: u audio adc: f s = 16 khz to 100 khz u voice adc: f s = 7 khz to 50 khz u audio dac: f s = 16 khz to 200 khz n separate power control for adc and dac n adc plus integrated high-pass ?lter to cancel dc offset n integrated digital ?lter plus dac n slave mode only applications n easy application UDA1384 multichannel audio coder-decoder rev. 02 17 january 2005 product data sheet
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 2 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 2.2 multiple format data interface n audio interface supports standard i 2 s-bus, msb-justi?ed, lsb-justi?ed and two multichannel formats n voice interface supports i 2 s-bus and mono channel formats 2.3 digital sound processing n control via l3-bus or i 2 c-bus: u channel independent digital logarithmic volume u digital de-emphasis for f s = 32 khz, 44.1 khz, 48 khz or 96 khz u soft or quick mute u output signal polarity control 2.4 advanced audio con?guration n inputs: u 4 single-ended audio inputs (2 stereo) with programmable gain ampli?ers u 1 single-ended voice input n outputs: u 6 differential audio outputs (3 stereo) n dsd mode to support stereo dsd playback n high linearity, wide dynamic range and low distortion n dac digital ?lter with selectable sharp or soft roll-off 3. applications n excellently suitable for multichannel home audio-video application 4. quick reference data table 1: quick reference data v ddd = v dda(ad) = v dda(da) = 3.3 v; t amb = 25 c; r l = 22 k w ; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dda(ad) adc analog supply voltage 2.7 3.3 3.6 v v dda(da) dac analog supply voltage 2.7 3.3 3.6 v v ddd digital supply voltage 2.7 3.3 3.6 v i dda(ad) adc analog supply current f adc = 48 khz - 30 - ma i dda(da) dac analog supply current f dac = 48 khz - 20 - ma i ddd digital supply current f adc =f dac = 48 khz; f voice = 48 khz -31-ma
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 3 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder [1] the input voltage can be up to 2 v (rms) when the current through the adc input pin is limited to approximately 1 ma by using a series resistor. [2] the input voltage to the adc scales proportionally with the power supply voltage. 5. ordering information i ddd(pd) digital supply current in power-down mode audio and voice adcs power-down -18-ma dac power-down - 14 - ma t amb ambient temperature - 20 - +85 c audio analog-to-digital converter d 0 digital output level at 0 db setting; 900 mv input [1] [2] - 2.5 - 1.2 - 0.7 db (thd+n)/s total harmonic distortion-plus-noise to signal ratio at - 1 dbfs - - 88 - 82 db at - 60 dbfs; a-weighted - - 37 - 30 db s/n signal-to-noise ratio code = 0; a-weighted 89 98 - db a cs channel separation - 100 - db digital-to-analog converter differential mode v o(rms) output voltage (rms value) at 0 dbfs digital input 1.9 2.0 2.1 v (thd+n)/s total harmonic distortion-plus-noise to signal ratio at 0 dbfs - - 98 - 89 db at - 60 dbfs; a-weighted - - 50 - 45 db s/n signal-to-noise ratio code = 0; a-weighted 100 110 - db a cs channel separation - 114 - db single-ended mode v o(rms) output voltage (rms value) at 0 dbfs digital input - 1.0 - v (thd+n)/s total harmonic distortion-plus-noise to signal ratio at 0 dbfs - - 88 - db at - 60 dbfs; a-weighted - - 45 - db s/n signal-to-noise ratio code = 0; a-weighted - 105 - db a cs channel separation - 110 - db table 1: quick reference data continued v ddd = v dda(ad) = v dda(da) = 3.3 v; t amb = 25 c; r l = 22 k w ; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. symbol parameter conditions min typ max unit table 2: ordering information type number package name description version UDA1384h qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 4 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 6. block diagram fig 1. block diagram mce639 pga adc 2l pll pll i 2 s-bus interface 3 hp filter decimation filter 6 21 20 22 30 37 40 24 23 vinl2 mcclk mcmode mcdata i2c_l3 bckda wsda 53 decimation filter dc-cancellation filter i 2 s-bus interface 2 l3-bus or i 2 c-bus control interface v dda(da) v ssa(da) interpolation filter volume, mute, de-emphasis noise shaper i 2 s-bus interface 1 v dda(ad) 9 v adcp 7 v adcn 1 v ref v ssa(ad) UDA1384 lna 10 vvoice pga adc 1l pga adc 2r pga adc 1r 2 vinl1 vout2n vout2p vout4n vout4p vout6n vout6p vout1n vout1p vout3n vout3p vout5n vout5p dac 2 34 - + 33 39 38 44 43 32 31 36 35 42 41 dac 4 - + dac 6 dac 1 dac 3 dac 5 - + - + adc clock test - + - + 25 datada1 26 datada2 27 datada3 13 dataad1 12 dataad2 14 bckad 11 test 4 vinr1 8 vinr2 19 sysclk 15 wsad 17 bckv 16 datav 18 wsv 28 29 v ddd v ssd
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 5 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration UDA1384h v ref vout2p vinl1 vout1n v ssa(ad) vout1p vinr1 i2c_l3 v dda(ad) v ddd vinl2 v ssd v adcn datada3 vinr2 datada2 v adcp datada1 vvoice bckda test wsda dataad2 vout6n dataad1 vout6p bckad vout5n wsad vout5p datav v ssa(da) bckv vout4n wsv vout4p sysclk v dda(da) mcmode vout3n mcclk vout3p mcdata vout2n 001aac311 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 table 3: pin description symbol pin type description v ref 1 aio adc reference voltage vinl1 2 aio adc 1 input left v ssa(ad) 3 agnd adc analog ground vinr1 4 aio adc 1 input right v dda(ad) 5 as adc analog supply voltage vinl2 6 aio adc 2 input left v adcn 7 aio adc reference voltage n vinr2 8 aio adc 2 input right v adcp 9 aio adc reference voltage p vvoice 10 aio voice adc input test 11 did test input; must be connected to digital ground (v ssd ) in application dataad2 12 do adc 2 data output dataad1 13 do adc 1 data output bckad 14 dis adc bit clock input wsad 15 di adc word select input
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 6 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder [1] see t ab le 4 . datav 16 do voice data output bckv 17 dis voice bit clock input wsv 18 dio voice word select input or output sysclk 19 dis system clock input: 256f s , 384f s , 512f s or 768f s mcmode 20 di l3-bus l3mode input or i 2 c-bus dac mute control input mcclk 21 dis l3-bus l3clock input or i 2 c-bus scl input mcdata 22 iic l3-bus l3data input and output or i 2 c-bus sda input and output wsda 23 di dac word select input bckda 24 dis dac bit clock input datada1 25 di dac channel 1 and channel 2 data input datada2 26 di dac channel 3 and channel 4 data input datada3 27 di dac channel 5 and channel 6 data input v ssd 28 dgnd digital ground v ddd 29 ds digital supply voltage i2c_l3 30 di selection input for l3-bus or i 2 c-bus control vout1p 31 aio dac 1 positive output vout1n 32 aio dac 1 negative output vout2p 33 aio dac 2 positive output vout2n 34 aio dac 2 negative output vout3p 35 aio dac 3 positive output vout3n 36 aio dac 3 negative output v dda(da) 37 as dac analog supply voltage vout4p 38 aio dac 4 positive output vout4n 39 aio dac 4 negative output v ssa(da) 40 agnd dac analog ground vout5p 41 aio dac 5 positive output vout5n 42 aio dac 5 negative output vout6p 43 aio dac 6 positive output vout6n 44 aio dac 6 negative output table 4: pin types type description agnd analog ground aio analog input and output as analog supply dgnd digital ground di digital input did digital input with internal pull-down resistor dio digital input and output table 3: pin description continued symbol pin type description
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 7 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 8. functional description 8.1 system clock the UDA1384 operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice adc) or the word clock. the audio adc part, the voice adc part and the dac part can operate at different sampling frequencies (dac-ws and adc-ws modes) as well as a common frequency (sysclk, wsda and dsd modes). the voice adc part supports a sampling frequency up to 50 khz and the audio adc supports a sampling frequency up to 100 khz. the dac sampling frequency range is extended up to 200 khz with the range above 100 khz being supported through 192 khz sampling mode, which halves the oversampling ratio of sysclk and internal clocks. the mode of operation of the audio and voice channels can be set via the l3-bus or i 2 c-bus microcontroller interface and are summarized in t ab le 5 and t ab le 6 . when applied, the system clock must be locked in frequency to the corresponding digital interface clocks. the voice adc part can either receive or generate the wsv signal as shown in t ab le 6 . dis digital schmitt-triggered input do digital output ds digital supply iic input and open-drain output for i 2 c-bus table 4: pin types continued type description table 5: audio adc and dac operating clock mode mode audio adc audio dac clock frequency clock frequency sysclk sysclk 256f s , 384f s , 512f s or 768f s sysclk 256f s , 384f s , 512f s or 768f s sysclk 128f s , 192f s , 256f s or 384f s ; 192 khz sampling mode dac-ws sysclk 256f s , 384f s , 512f s or 768f s wsda 1f s adc-ws wsad 1f s sysclk 256f s , 384f s , 512f s or 768f s sysclk 128f s , 192f s , 256f s or 384f s ; 192 khz sampling mode wsda wsda 1f s wsda 1f s dsd sysclk 44.1 khz 512 sysclk 44.1 khz 512 table 6: voice adc operating clock mode mode voice adc bit clock frequency (bckv) word select (wsv) wsv-in input: 32f s , 64f s , 128f s or 256f s input wsv-out input: 32f s , 64f s , 128f s or 256f s output
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 8 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 8.2 audio analog-to-digital converter (audio adc) the audio analog-to-digital front-end of the UDA1384 consists of 4-channel single-ended adcs with programmable gain stage (from 0 db to 24 db with 3 db steps), controlled via the microcontroller interface. using the pga feature, it is possible to accept an input signal of 900 mv (rms) or 1.8 v (rms) if an external resistor of 10 k w is used in series. the schematic of audio adc front-end is shown in figure 3 . 8.3 voice analog-to-digital converter (voice adc) the voice analog-to-digital front-end of the UDA1384 consists of a single-channel single-ended adc with a ?xed gain (26 db) low noise ampli?er (lna). together with the digital variable gain ampli?cation stage, the voice adc provides optimal processing and reproduction of the microphone signal. the supported sampling frequency range is from 7 khz to 50 khz. power-down of the lna and the adc can be controlled separately. 8.4 decimation ?lter of audio adc the decimation from 64f s is performed in two stages. the ?rst stage realizes characteristics with a decimation factor of 8. the second stage consists of three half-band ?lters, each decimating by a factor of 2. the ?lter characteristics are shown in t ab le 7 . 8.5 decimation ?lter of voice adc the voice adc decimation ?lter is realized with the combination of a finite impulse response (fir) ?lter and in?nite impulse response (iir) ?lter for shorter group delay. the ?lter characteristics are shown in t ab le 8 . during the power-on sequence, the output of the adc is hard muted for a certain period. this hard-mute time can be chosen between 1024 samples and 2048 samples. fig 3. schematic of audio adc front-end mgu582 v ref adc v dda = 3.3 v vinl, vinr 10 k w (0 db setting) 10 k w 10 k w input signal 2 v (rms) table 7: decimation ?lter characteristics (audio adc) item condition value (db) pass-band ripple 0f s to 0.45f s 0.01 pass-band droop 0.45f s - 0.2 stop band > 0.55f s - 70 dynamic range 0f s to 0.45f s > 135 x sin x ---------- ? ?? 4
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 9 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 8.6 interpolation ?lter of dac the digital interpolation ?lter interpolates from 1f s to 128f s (or to 64f s in the 192 khz sampling mode) by cascading fir ?lters, and has two sets of ?lter coef?cients for sharp and slow roll-off as given in t ab le 9 and t ab le 10 . 8.7 noise shaper of dac the 3rd-order noise shaper operates at either 128f s or 64f s (in the 192 khz sampling mode), and converts the 24-bit input signal into a 5-bit signal stream. the noise shaper shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. 8.8 digital mixer the UDA1384 has 6 digital mixers inside the interpolator (see figure 4 ). the adc signals can be mixed with the i 2 s-bus input signals. the mixing of the adc signals can be selected by the bits mix[1:0]. table 8: decimation ?lter characteristics (voice adc) item condition value (db) pass-band ripple 0f s to 0.45f s 0.05 pass-band droop 0.45f s - 0.2 stop band > 0.55f s - 65 dynamic range 0f s to 0.45f s > 110 table 9: interpolation ?lter characteristics (sharp roll-off) item condition value (db) pass-band ripple 0f s to 0.45f s 0.002 stop band > 0.55f s - 75 dynamic range 0f s to 0.45f s > 135 table 10: interpolation ?lter characteristics (slow roll-off) item condition value (db) pass-band ripple 0f s to 0.22f s 0.002 pass-band droop 0.45f s - 3.1 stop band > 0.78f s - 94 dynamic range 0f s to 0.22f s > 135
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 10 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 8.9 audio digital-to-analog converters the audio digital-to-analog front-end of the UDA1384 consists of 6-channel differential sdacs: an sdac is a multi-bit dac based upon switched resistors. to minimize data dependent modulation effects, a dynamic element matching (dem) algorithm scrambler circuit and dc current compensation circuit are implemented with the sdac. 8.10 power-on reset the UDA1384 has an internal power-on reset circuit which initializes the device (see figure 5 ). all the digital sound processing features and the system controlling features are set to their default values in the l3-bus and the i 2 c-bus modes. the reset time (see figure 6 ) is determined by an external capacitor which is connected between pin v ref and ground. the reset time should be at least 250 m s for v ref < 1.25 v. when v dda(ad) is switched off, the device will be reset again for v ref < 0.75 v. during the reset time, the system clock should be running. fig 4. block diagram of dac mixer mgw786 mix [ 1:0 ] dis [ 1:0 ] ics [ 1:0 ] from adc mixer volume mixer mute dac1 1f s volume de-emphasis mute dac2 same as above dac3 same as above dac4 same as above dac5 same as above dac6 same as above interpolation filter ch1 mixer input ch2 ch3 ch4 from i 2 s-bus datada1 datada2 datada3 +
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 11 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 8.11 audio digital interface the following audio formats can be selected via the microcontroller interface: ? i 2 s-bus format with data word length of up to 24 bits ? msb-justi?ed format with data word length of up to 24 bits ? lsb-justi?ed format with data word length of 16 bits, 20 bits or 24 bits ? multichannel formats with data word length of 20 bits or 24 bits. the used data lines are dataad1 and datada1 and the sampling frequency must be below 50 khz the formats are illustrated in figure 7 and figure 8 . fig 5. power-on reset circuit fig 6. power-on reset timing v dda(ad) v ref mgu585 c1 > 10 m f reset circuit 9 k w 9 k w 3.3 v ddd (v) 0 t 3.3 v dda(ad) (v) 0 t v ref (v) 1.65 1.25 0.75 t rst 0 t mgu586 > 250 m s
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 12 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder fig 7. formats of input and output data (single-channel) 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb msb msb b2 2 1 > = 8 12 3 left i 2 s-bus format ws bck data right 3 > = 8 msb b2 mgt020 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb-justified format ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 b2 > = 8 > = 8 bck data
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 13 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder (1) format 1. (2) format 2. fig 8. formats of input and output data (multichannel) mgu588 multichannel format 20 bits ws bck data 2 122 21 ch1 42 41 61 msb lsb msb msb lsb ch3 lsb ch5 2 122 21 ch2 42 41 61 msb lsb msb multichannel format 24 bits (1) bck ws ws data 2 126 25 ch1 50 49 73 msb lsb msb msb lsb ch3 lsb ch5 2 126 25 ch2 50 49 73 msb lsb msb msb lsb ch4 lsb ch6 multichannel format 24 bits (2) bck data 126 25 ch1 50 49 74 msb lsb msb 73 97 ch3 msb lsb ch5 lsb 126 25 ch2 50 49 74 msb lsb msb 73 97 ch4 msb lsb ch6 lsb msb lsb ch4 lsb ch6
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 14 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 8.12 voice digital interface the following voice formats can be selected via the microcontroller interface: ? i 2 s-bus format with data word length of up to 20 bits. the left and the right channels contain the same data. ? mono channel format with data word length of up to 20 bits. the formats are illustrated in figure 9 . 8.13 dsd mode the UDA1384 can receive 2.8224 mhz dsd signals and generate 88.2 khz multibit pcm signals as well as analog signal outputs. the con?guration of the UDA1384 in the dsd mode is shown in figure 10 . fig 9. voice digital interface formats mgu587 msb msb b2 2 1 3 8 12 3 left i 2 s-bus format ws bck data right 3 3 8 msb b2 msb b2 2 1 3 8 123 mono channel format ws bck data msb b2 fig 10. dsd mode mgu584 left channel 2.8224 mhz dsd right channel 5.6448 mhz 88.2 khz bckad datada3 datada2 wsad wsda 88.2 khz 22.5792 mhz 5.6448 mhz i 2 s-bus (left and right) 88.2 khz pcm data datada1 dataad1 bckda sysclk dac + - interpolation noise shaping i 2 s-bus interface 2 decimation filter i 2 s-bus interface 1 v out1n v out1p left channel dac + - v out2n v out2p right channel analog output
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 15 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 8.14 microcontroller interface mode the microcontroller interface mode can be selected as shown in t ab le 11 : ? l3-bus mode when pin i2c_l3 = low ? i 2 c-bus mode when pin i2c_l3 = high all the features are accessible with the i 2 c-bus interface protocol as with the l3-bus interface protocol. the detailed description of the device operation in the l3-bus mode and i 2 c-bus mode is given in section 9 and section 10 , respectively. 9. l3-bus interface 9.1 general the UDA1384 has an l3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. the exchange of data and control information between the microcontroller and the UDA1384 is lsb ?rst and is accomplished through a serial hardware l3-bus interface comprising the following pins: ? mcclk: clock line with signal l3clock ? mcdata: data line with signal l3data ? mcmode: mode line with signal l3mode the l3-bus format has two modes of operation: ? address mode ? data transfer mode the address mode is used to select a device for a subsequent data transfer. the address mode is characterized by signal l3mode = low and a burst of 8 pulses for signal l3clock, accompanied by 8 bits (see figure 11 ). table 11: pin function in the l3-bus or i 2 c-bus mode pin level on pin i2c_l3 low high l3-bus mode signal i 2 c-bus mode signal mcclk l3clock scl mcdata l3data sda mcmode l3mode qmute table 12: qmute signal qmute function low no muting high muting
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 16 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder the data transfer mode is characterized by signal l3mode = high and is used to transfer one or more bytes representing a register address, instruction or data. basically, two types of data transfers can be de?ned: ? write action: data transfer to the device ? read action: data transfer from the device. 9.2 device addressing the device address consists of one byte with: ? data operating mode (dom) bits 0 and 1 representing the type of data transfer (see t ab le 13 ) ? address bits 2 to 7 representing a 6-bit device address. the address of the UDA1384 is 01 0100 (bits 2 to 7). 9.3 register addressing after sending the device address (including dom bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. basically, there are 3 methods for register addressing: 1. addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see figure 11 ). 2. addressing for prepare read: bit is logic 1, indicating that data will be read from the register (see figure 12 ). 3. addressing for data read action. here, the device returns a register address prior to sending data from that register. when bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid (see figure 12 ). table 13: selection of data transfer dom transfer bit 1 bit 0 0 0 not used 0 1 not used 1 0 write data or prepare read 1 1 read data
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 17 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder fig 11. data write mode mbl567 l3clock l3mode l3data 0 write device address dom bits register address data byte 1 data byte 2 10 fig 12. data read mode mbl565 l3clock l3mode l3data 0 read valid/invalid device address prepare read sent by the device dom bits register address device address requesting register address data byte 1 data byte 2 111 0/1 1
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 18 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 9.4 data write mode the data write mode is explained in the signal diagram of figure 11 . for writing data to a device, 4 bytes must be sent (see t ab le 14 ): 1. byte 1 starting with 01 for signalling the write action to the device, followed by the device address 01 0100 2. byte 2 starting with a 0 for signalling the write action, followed by 7 bits indicating the destination address in binary format with bit a6 being the msb and bit a0 being the lsb 3. byte 3 with bit d15 being the msb 4. byte 4 with bit d0 being the lsb it should be noted that each time a new destination register address needs to be written, the device address must be sent again. 9.5 data read mode to read data from the device, a prepare read must ?rst be done and then data read. the data read mode is explained in the signal diagram of figure 12 . for reading data from a device, the following 6 bytes are involved (see t ab le 15 ): 1. byte 1 with the device address, including 01 for signalling the write action to the device. 2. byte 2 is sent with the register address from which data needs to be read. this byte starts with a 1, which indicates that there will be a read action from the register, followed by 7 bits for the destination address in binary format, with bit a6 being the msb and bit a0 being the lsb. 3. byte 3 with the device address, including 11 is sent to the device. the 11 indicates that the device must write data to the microcontroller. 4. byte 4 sent by the device to the bus, with the (requested) register address and a ?ag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1). 5. byte 5 sent by the device to the bus, with the data information in binary format, with bit d15 being the msb. 6. byte 6 sent by the device to the bus, with the data information in binary format, with bit d0 being the lsb. table 14: l3-bus write data byte l3-bus mode action first in time latest in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 01010100 2 data transfer register address 0 a6a5a4a3a2a1a0 3 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 4 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 19 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 10. i 2 c-bus interface 10.1 general the UDA1384 has an i 2 c-bus microcontroller interface. all the features are accessible with the i 2 c-bus interface protocol. in the i 2 c-bus mode, the dac mute function is accessible via pin mcmode with signal qmute. the exchange of data and control information between the microcontroller and the UDA1384 is accomplished through a serial hardware interface comprising the following pins as shown in t ab le 11 : ? mcclk: clock line with signal scl ? mcdata: data line with signal sda 10.2 characteristics of the i 2 c-bus the bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to the supply voltage v dd via a pull-up resistor when connected to the output stages of a microcontroller. for a 400 khz ic, the recommendation for this type of bus from philips semiconductors must be followed (e.g. up to loads of 200 pf on the bus a pull-up resistor can be used, between 200 pf and 400 pf a current source or switched resistor must be used). data transfer can only be initiated when the bus is not busy. 10.3 bit transfer one data bit is transferred during each clock pulse (see figure 13 ). the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. the maximum clock frequency is 400 khz. to be able to run on this high frequency, all the inputs and outputs connected to this bus must be designed for this high-speed i 2 c-bus according to the philips speci?cation. table 15: l3-bus read data byte l3-bus mode action first in time latest in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 01010100 2 data transfer register address 1 a6a5a4a3a2a1a0 3 address device address 11010100 4 data transfer register address 0 or 1a6a5a4a3a2a1a0 5 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 6 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 20 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 10.4 byte transfer each byte (8 bits) is transferred with the msb ?rst (see t ab le 16 ). 10.5 data transfer a device generating a message is a transmitter; a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. 10.6 start and stop conditions both data and clock line will remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is de?ned as a start condition (s); see figure 14 . a low-to-high transition of the data line while the clock is high is de?ned as a stop condition (p). 10.7 acknowledgment the number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit (see figure 15 ). at the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. fig 13. bit transfer on the i 2 c-bus mbc621 data line stable; data valid change of data allowed sda scl table 16: byte transfer bit number msb lsb 76543210 fig 14. start and stop conditions on the i 2 c-bus mbc622 sda scl p stop condition sda scl s start condition
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 21 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder a slave receiver which is addressed, must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. 10.8 device address before any data is transmitted on the i 2 c-bus, the device which should respond is addressed ?rst. the addressing is always done with byte 1 transmitted after the start procedure. the UDA1384 acts as a slave receiver or a slave transmitter. therefore, the clock signal scl is only an input signal. the data signal sda is a bidirectional line. the UDA1384 device address is shown in t ab le 17 . 10.9 register address the register addresses in the i 2 c-bus mode are the same as in the l3-bus mode. the register addresses are de?ned in section 11 . 10.10 write and read data the i 2 c-bus con?gurations for a write and read cycle are shown in t ab le 18 and t ab le 19 , respectively. fig 15. acknowledge on the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master table 17: i 2 c-bus device address of UDA1384 device address r/ w a6 a5 a4 a3 a2 a1 a0 00110000/1
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 22 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder the write cycle is used to write groups of two bytes to the internal registers for the settings. it is also possible to read the registers for the device status information. 10.11 write cycle the i 2 c-bus con?guration for a write cycle is shown in t ab le 18 . the write cycle is used to write the data to the internal registers. the device and register addresses are one byte each, the setting data is always a pair of two bytes. the format of the write cycle is as follows: 1. the microcontroller starts with a start condition (s). 2. the ?rst byte (8 bits) contains the device address 0011 000 and a logic 0 (write) for the r/ w bit. 3. this is followed by an acknowledge (a) from the UDA1384. 4. after this the microcontroller writes the 8-bit register address (addr) where the writing of the register content of the UDA1384 must start. 5. the UDA1384 acknowledges this register address (a). 6. the microcontroller sends 2 bytes data with the most signi?cant (ms) byte ?rst and then the least signi?cant (ls) byte. after each byte an acknowledge is followed from the UDA1384. 7. if repeated groups of 2 bytes data are transmitted, then the register address is auto incremented. after each byte an acknowledge is followed from the UDA1384. 8. finally, the UDA1384 frees the i 2 c-bus and the microcontroller can generate a stop condition (p). [1] auto increment of register address. 10.12 read cycle the read cycle is used to read the data values from the internal registers. the i 2 c-bus con?guration for a read cycle is shown in t ab le 19 . the format of the read cycle is as follows: 1. the microcontroller starts with a start condition (s). 2. the ?rst byte (8 bits) contains the device address 0011 000 and a logic 0 (write) for the r/ w bit. 3. this is followed by an acknowledge (a) from the UDA1384. 4. after this the microcontroller writes the 8-bit register address (addr) where the reading of the register content of the UDA1384 must start. 5. the UDA1384 acknowledges this register address. 6. then the microcontroller generates a repeated start (sr). table 18: master transmitter writes to UDA1384 registers in the i 2 c-bus mode device address r/ w register address data 1 data 2 [1] data n [1] s 0011 000 0 a addr a ms1 a ls1 a ms2 a ls2 a msn a lsn a p a = acknowledge from UDA1384
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 23 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 7. then the microcontroller generates the device address 0011 000 again, but this time followed by a logic 1 (read) of the r/ w bit. an acknowledge is followed from the UDA1384. 8. the UDA1384 sends 2 bytes data with the most signi?cant (ms) byte ?rst and then the least signi?cant (ls) byte. after each byte an acknowledge is followed from the microcontroller (master). 9. if repeated groups of 2 bytes are transmitted, then the register address is auto incremented. after each byte an acknowledge is followed from the microcontroller. 10.the microcontroller stops this cycle by generating a negative acknowledge (na). 11.finally, the UDA1384 frees the i 2 c-bus and the microcontroller can generate a stop condition (p). [1] auto increment of register address. 11. register mapping in this chapter the register addressing and mapping of the microcontroller interface of the UDA1384 is given. in t ab le 20 an overview of the register mapping is given. in t ab le 21 the actual register mapping is given and the register de?nitions are explained in section 11.3 to section 11.14 . 11.1 address mapping table 19: master transmitter reads from the UDA1384 registers in the i 2 c-bus mode device address r/ w register address device address r/ w data 1 data 2 [1] data n [1] s 0011 000 0 a addr a sr 0011 000 1 a ms1 a ls1 a ms2 a ls2 a msn a lsn na p a = acknowledge from UDA1384 a = acknowledge from master table 20: overview of register mapping address function system settings 00h system 01h audio adc and dac subsystem 02h voice adc system status (read out registers) 0fh status outputs interpolator settings 10h dac channel and feature selection 11h dac feature control 12h dac channel 1 13h dac channel 2 14h dac channel 3 15h dac channel 4
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 24 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 16h dac channel 5 17h dac channel 6 18h dac mixing channel 1 19h dac mixing channel 2 1ah dac mixing channel 3 1bh dac mixing channel 4 1ch dac mixing channel 5 1dh dac mixing channel 6 adc input ampli?er gain settings 20h audio adc input ampli?er gain 21h voice adc input ampli?er gain supplemental settings 30h supplemental settings 1 31h supplemental settings 2 table 20: overview of register mapping continued address function
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 25 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.2 register mapping table 21: UDA1384 register mapping [1] add function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 system settings 00h system rst [2] vfs1 vfs0 vce vap dsd sc1 sc0 op1 op0 fs1 fs0 ace adp dce dap - 001000000011010 01h audio adc and dac subsystem dc pab paa mtb mta aif2 aif1 aif0 dag fil dvd dis1 dis0 dif2 dif1 dif0 1 000000000000000 02h voice adc system - ------- bck1 bck0 wsm vh1 vh0 pva mtv vif 0 000000001101000 status (read out only) 0fh status outputs - ---------vsas1as0ds2ds1ds0 interpolator settings 10h dac channel and feature selection mix1 mix0 mc5 mc4 mc3 mc2 mc1 mc0 sel1 sel0 cs5 cs4 cs3 cs2 cs1 cs0 0 000000000000000 11h dac feature control ics1 ics0 de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 000000000000000 12h dac channel 1 ics1 ics0 de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 000000000000000 13h dac channel 2 - - de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 000000000000000 14h dac channel 3 ics1 ics0 de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 000000000000000 15h dac channel 4 - - de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 000000000000000 16h dac channel 5 ics1 ics0 de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 000000000000000 17h dac channel 6 - - de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 000000000000000 18h dac mixing channel 1 ics1 ics0 ---pdmtqmvc7vc6vc5vc4vc3vc2vc1vc0 0 000000000000000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 26 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder [1] when writing new settings via the l3-bus interface, the default values should always be set to warrant correct operation. re ad access to the dac features register 11h will not return valid data. [2] when bit rst is set to logic 1, the default values are set to all the registers as shown in t ab le 21 . when start-up, all the registers in 00h are initialized as the default values and the mute control bits mta, mtb, mtv, mt and qm are set to logic 1. all other registers have non ?xed values. 19h dac mixing channel 2 - ----pdmtqmvc7vc6vc5vc4vc3vc2vc1vc0 0 000000000000000 1ah dac mixing channel 3 ics1 ics0 ---pdmtqmvc7vc6vc5vc4vc3vc2vc1vc0 0 000000000000000 1bh dac mixing channel 4 - ----pdmtqmvc7vc6vc5vc4vc3vc2vc1vc0 0 000000000000000 1ch dac mixing channel 5 ics1 ics0 ---pdmtqmvc7vc6vc5vc4vc3vc2vc1vc0 0 000000000000000 1dh dac mixing channel 6 - ----pdmtqmvc7vc6vc5vc4vc3vc2vc1vc0 0 000000000000000 adc input ampli?er gain settings 20h adc 1 and adc 2 input ampli?er gain - ---ib3ib2ib1ib0----ia3ia2ia1ia0 0 000000000000000 21h voice adc input ampli?er gain - ----------iv4iv3iv2iv1iv0 - ------- 00000000 supplemental settings 30h supplemental settings 1 - -------pdt------- 0 000000000000000 31h supplemental settings 2 - -------- dith2 dith1 dith0 - - vmtp pdlna 0 000000000000000 table 21: UDA1384 register mapping [1] continued add function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 27 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.3 system settings table 22: system register (address 00h) bit allocation bit 15 14 13 12 11 10 9 8 symbol rst vfs1 vfs0 vce vap dsd sc1 sc0 reset - 0010000 access read and write bit 7 6 5 4 3 2 1 0 symbol op1 op0 fs1 fs0 ace adp dce dap reset 00011010 access read and write table 23: description of system register bits bit symbol description 15 rst reset. bit rst initializes the l3-bus registers with the default settings. 1 = reset to default settings 0 = no reset 14 to 13 vfs[1:0] voice adc sampling frequency. a 2-bit value to select the voice adc sampling frequency. default 00. see t ab le 24 . 12 vce voice adc clock enable. 1 = clock enabled (default) 0 = clock disabled 11 vap voice adc power control . bit vap is to reduce the power consumption of the voice adc. 1 = state is power-on 0 = state is power-off (default) 10 dsd dsd mode selection. bit dsd selects the dsd mode. 1 = dsd mode 0 = normal mode (default) 9 to 8 sc[1:0] system clock frequency. a 2-bit value to select the used external clock frequency. 128f s system clock for the dac can be used by setting bit dvd = 1. default 00. see t ab le 25 . 7 to 6 op[1:0] operating mode selection. a 2-bit value to select the operation mode of the audio adc and dac. default 00. see t ab le 26 . 5 to 4 fs[1:0] sampling frequency. a 2-bit value to select the sampling frequency of the audio adc and dac in the ws mode. default 01. see t ab le 27 . 3ace adc clock enable. bit ace enables the audio adc clock 1 = clock enabled (default) 0 = clock disabled 2 adp adc power control . bit adp is to reduce the power consumption of the audio adc. 1 = state is power-on 0 = state is power-off (default)
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 28 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 1 dce dac clock enable. bit dce enables the dac clock. 1 = clock enabled (default) 0 = clock disabled 0dap dac power control . bit dap is to reduce the power consumption of the dac. 1 = state is power-on 0 = state is power-off (default) table 24: voice adc sampling frequency bits vfs1 vfs0 function 0 0 6.25 khz to 12.5 khz (default) 0 1 12.5 khz to 25 khz 1 0 25 khz to 50 khz 1 1 reserved table 25: system clock frequency bits sc1 sc0 adc dac remark bit dvd = 0 bit dvd = 1 0 0 256f s 256f s 128f s default 0 1 384f s 384f s 192f s 1 0 512f s 512f s 256f s 1 1 768f s 768f s 384f s table 26: operating mode bits op1 op0 adc mode dac mode remark 0 0 sysclk (256f s , 384f s , 512f s or 768f s ) sysclk (128f s , 256f s , 384f s , 512f s or 768f s ) default 0 1 sysclk (256f s , 384f s , 512f s or 768f s ) wsda (1f s ) 1 0 wsad (1f s ) sysclk (128f s , 256f s , 384f s , 512f s or 768f s ) 1 1 wsda (1f s ) wsda (1f s ) table 27: audio adc and dac sampling frequency bits fs1 fs0 function 0 0 12.5 khz to 25 khz 0 1 25 khz to 50 khz (default) 1 0 50 khz to 100 khz 1 1 100 khz to 200 khz table 23: description of system register bits continued bit symbol description
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 29 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.4 audio adc and dac subsystem settings table 28: audio adc and dac subsystem register (address 01h) bit allocation bit 15 14 13 12 11 10 9 8 symbol dc pab paa mtb mta aif2 aif1 aif0 reset 10000000 access read and write bit 7 6 5 4 3 2 1 0 symbol dag fil dvd dis1 dis0 dif2 dif1 dif0 reset 00000000 access read and write table 29: description of the audio adc and dac subsystem register bit bit symbol description 15 dc adc dc-?lter. bit dc enables the digital dc-?lter of the adc. 1 = dc-?ltering is active (default) 0 = no dc-?ltering 14 pab polarity adc 2 control. bit pab controls the adc 2 polarity. 1 = polarity is inverted 0 = polarity is not-inverted (default) 13 paa polarity adc 1 control. bit paa controls the adc 1 polarity. 1 = polarity is inverted 0 = polarity is not-inverted (default) 12 mtb mute adc 2. bit mtb enables the digital mute of adc 2. 1 = adc 2 is soft muted 0 = adc 2 is not muted (default) 11 mta mute adc 1. bit mta enables the digital mute of adc 1. 1 = adc 1 is soft muted 0 = adc 1 is not muted (default) 10 to 8 aif[2:0] adc output data interface format. a 3-bit value to select the used data format to the i 2 s-bus adc output interface. default 000. see t ab le 30 . 7dag dac gain switch. bit dag selects the dac gain. 1=gain=6db 0 = gain = 0 db (default) 6 fil filter selection. bit fil selects the interpolation ?lter characteristics. 1 = slow roll-off 0 = sharp roll-off (default) 5dvd 192 khz sampling mode selection. bit dvd selects the oversampling rate of the noise shaper. 1 = 64f s rate; used for 192 khz and 176.4 khz sampling frequencies 0 = 128f s rate (default) 4 to 3 dis[1:0] data interface selection. a 2-bit value to select the data interface connection. default 00. see t ab le 31 . 2 to 0 dif[2:0] dac input data interface format. a 3-bit value to select the used data format to the i 2 s-bus dac input interface. default 000. see t ab le 30 .
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 30 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.5 voice adc system settings table 30: data interface format bits aif2 aif1 aif0 function dif2 dif1 dif0 000i 2 s-bus format (default) 0 0 1 lsb-justi?ed format, 16 bits 0 1 0 lsb-justi?ed format, 20 bits 0 1 1 lsb-justi?ed format, 24 bits 1 0 0 msb-justi?ed format 1 0 1 multichannel format, 20 bits 1 1 0 multichannel format, 24 bits (format 1) 1 1 1 multichannel format, 24 bits (format 2) table 31: data interface selection bits dis1 dis0 input to dac 0 0 datada1 to dac channel 1 and 2, datada2 to dac channel 3 and 4, and datada3 to dac channel 5 and 6 (default) 0 1 datada1 to dac channels 1 to 6 1 0 datada2 to dac channels 1 to 6 1 1 datada3 to dac channels 1 to 6 table 32: voice adc system register (address 02h) bit allocation bit 15 14 13 12 11 10 9 8 symbol -------- reset -------- access read and write bit 7 6 5 4 3 2 1 0 symbol bck1 bck0 wsm vh1 vh0 pva mtv vif reset 01101000 access read and write table 33: description of the voice adc system register bits bit symbol description 15 to 8 - default 0000 0000 7 to 6 bck[1:0] bck frequency of voice adc. a 2-bit value to select the bck frequency of the voice adc in the wsv-out mode. default 01. see t ab le 34 . 5 wsm wsv mode selection. bit wsm selects the wsv mode of the voice adc 1 = wsv-in mode (default) 0 = wsv-out mode 4 to 3 vh[1:0] voice adc high-pass ?lter setting. a 2-bit value to enable the high-pass ?lter of the voice adc. default 01. see t ab le 35 .
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 31 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 2pva polarity voice adc control. bit pva controls the voice adc polarity. 1 = polarity is inverted 0 = polarity is not-inverted (default) 1 mtv mute voice adc. bit mtv enables the digital mute of the voice adc. 1 = adc 1 is soft muted 0 = adc 1 is not muted (default) 0 vif voice adc interface format. bit vif selects the data interface format of the voice adc. 1 = mono-channel format 0=i 2 s-bus format (default) table 34: bck frequency of voice adc bits bck1 bck0 function 0 0 32f s 0 1 64f s (default) 1 0 128f s 1 1 256f s table 35: voice adc high-pass ?lter setting bits vh1 vh0 function 0 0 high-pass ?lter off 01f c = 0.00008f s (default) 10f c = 0.0125f s 11f c = 0.025f s table 33: description of the voice adc system register bits continued bit symbol description
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 32 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.6 status output register table 36: status output register (address 0fh) bit allocation bit 15 14 13 12 11 10 9 8 symbol -------- reset -------- access read only bit 7 6 5 4 3 2 1 0 symbol - - vs as1 as0 ds2 ds1 ds0 reset -------- access read only table 37: description of status output register bits bit symbol description 15 to 6 - not used 5vs voice adc status. bit vs indicates the hard mute status of the voice adc. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 4 as1 adc 2 status. bit as1 indicates the hard mute status of adc 2. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 3 as0 adc 1 status. bit as0 indicates the hard mute status of adc 1. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 2 ds2 dac channel 5 and 6 status. bit ds2 indicates the hard mute status of dac channel 5 and 6. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 1 ds1 dac channel 3 and 4 status. bit ds1 indicates the hard mute status of dac channel 3 and 4. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 0 ds0 dac channel 1 and 2 status. bit ds0 indicates the hard mute status of dac channel 1 and 2. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 33 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.7 dac channel selection table 38: dac channel select register (address 10h) bit allocation bit 15 14 13 12 11 10 9 8 symbol mix1 mix0 mc5 mc4 mc3 mc2 mc1 mc0 reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol sel1 sel0 cs5 cs4 cs3 cs2 cs1 cs0 reset 00000000 access read and write table 39: description of dac channel select register bits bit symbol description 15 to 14 mix[1:0] dac mixer setting. a 2-bit value to enable the dac mixer. default 00. see t ab le 40 . 13 to 8 mc[5:0] dac mixing channel selection. a group of 6 enable bits to make dac mixing channels ready for receiving feature settings through register address 11h. only selected registers accept new settings. default 00 0000 (no channel ready). see t ab le 41 . 7 and 6 sel[1:0] feature selection. a 2-bit value to select the features to be set through register address 11h. when the feature settings are written, only selected feature settings are changed and non selected features are kept unchanged. default 00. see t ab le 42 . 5 to 0 cs[5:0] dac channel selection. a group of 6 enable bits to make dac channel ready for receiving feature settings through register address 11h. default 00 0000 (no channel ready). see t ab le 41 . table 40: dac mixer setting bits mix1 mix0 function 0 0 no mixing (default) 0 1 no mixing 1 0 mixing adc 1 1 1 mixing adc 2 table 41: dac channel and mixing channel selection bits mc5 mc4 mc3 mc2 mc1 mc0 function cs5 cs4 cs3 cs2 cs1 cs0 000000no channel ready (default) 000001 channel 1 selected :::::: 001010 channel 2 and channel 4 selected :::::: 111111 all channels selected
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 34 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.8 dac features settings table 42: feature selection bits sel1 sel0 function 0 0 all features (default) 0 1 volume 1 0 mute and quick mute 1 1 de-emphasis, polarity and input channel selection table 43: dac features register (address 11h) bit allocation bit 15 14 13 12 11 10 9 8 symbol ics1 ics0 de2 de1 de0 pd mt qm reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset 00000000 access read and write table 44: description of dac features register bits bit symbol description 15 to 14 ics[1:0] input channel selection. a 2-bit value to select the input channels. as the controlled channels are paired off, this 2-bit value must be written to each odd channel register. default 00. see t ab le 45 . 13 to 11 de[2:0] de-emphasis setting. a 3-bit value to enable the digital de-emphasis ?lter. default 000. see t ab le 46 . 10 pd polarity dac control. bit pd controls the dac polarity. 1 = polarity is inverted 0 = polarity is not-inverted (default) 9mt muting. bit mt enables the digital mute. all the dac outputs are muted at start-up. it is necessary to explicitly switch off for the audio output by means of bit mt. 1 = muting (start-up) 0 = no muting (default) 8qm quick mute. bit qm sets the quick mute mode. 1 = quick mute mode 0 = soft mute mode (default) 7 to 0 vc[7:0] interpolator volume control. an 8-bit value to program the volume attenuation of each channel. the range is from 0 db to - 53 db in steps of 0.25 db, from - 53 db to - 80 db in steps of 3 db and - db. default 0000 0000. see t ab le 47 .
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 35 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder table 45: input channel selection bits ics1 ics0 input to dac output 0 0 left channel input data to odd channel output; right channel input data to even channel output 0 1 left channel input data to odd and even channel outputs 1 0 right channel input data to odd and even channel outputs 1 1 left channel input data to even channel output; right channel input data to odd channel output table 46: de-emphasis bits de2 de1 de0 function 0 0 0 no de-emphasis (default) 0 0 1 de-emphasis of 32 khz 0 1 0 de-emphasis of 44.1 khz 0 1 1 de-emphasis of 48 khz 1 0 0 de-emphasis of 96 khz 1 0 1 not used 1 1 0 not used 1 1 1 not used table 47: interpolator volume control bits vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 volume (db) 000000000 (default) 00000001 - 0.25 00000010 - 0.50 00000011 - 0.75 00000100 - 1.00 00000101 - 1.25 ::::::::: 11010100 - 53 11011000 - 56 11011100 - 59 11100000 - 62 11100100 - 65 11101000 - 68 11101100 - 71 11110000 - 74 11110100 - 77 11111000 - 80 11111100 - ::::::::: 11111111 -
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 36 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.9 dac channel 1 to channel 6 settings all the dac features which are written in register 11h are copied into the odd channel registers. all the dac features which are written in register 11h are copied into the even channel registers, except the bits ics[1:0]. 11.10 dac mixing channel settings all the dac features which are written in register 11h are copied into the odd mixing channel registers, except the bits de[2:0]. table 48: dac channel 1, 3 and 5 registers (address 12h, 14h and 16h) bit allocation bit 15 14 13 12 11 10 9 8 symbol ics1 ics0 de2 de1 de0 pd mt qm reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset 00000000 access read and write table 49: dac channel 2, 4 and 6 registers (address 13h, 15h and 17h) bit allocation bit 15 14 13 12 11 10 9 8 symbol - - de2 de1 de0 pd mt qm reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset 00000000 access read and write table 50: dac mixing channel 1, 3 and 5 registers (address 18h, 1ah and 1ch) bit allocation bit 15 14 13 12 11 10 9 8 symbol ics1 ics0 - - - pd mt qm reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset 00000000 access read and write
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 37 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder all the dac features which are written in register 11h are copied into the even channel registers, except the bits ics[1:0] and de[2:0]. 11.11 audio adc 1 and adc 2 input ampli?er gain settings table 51: dac mixing channel 2, 4 and 6 registers (address 19h, 1bh and 1dh) bit allocation bit 15 14 13 12 11 10 9 8 symbol -----pdmtqm reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset 00000000 access read and write table 52: audio adc input ampli?er gain register (address 20h) bit allocation bit 15 14 13 12 11 10 9 8 symbol ----ib3ib2ib1ib0 reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol ----ia3ia2ia1ia0 reset 00000000 access read and write table 53: description of audio adc input ampli?er gain register bits bit symbol description 15 to 12 - default 0000 11 to 8 ib[3:0] audio adc 2 input ampli?er gain. a 4-bit value to program the input ampli?er gain in steps of 3 db (9 settings). default 0000. see t ab le 54 . 7 to 4 - default 0000 3 to 0 ia[3:0] audio adc 1 input ampli?er gain. a 4-bit value to program the input ampli?er gain in steps of 3 db (9 settings). default 0000. see t ab le 54 . table 54: audio adc input ampli?er gain bits ia3 ia2 ia1 ia0 gain (db) ib3 ib2 ib1 ib0 00000 (default) 0001+3 0010+6 0011+9 0100+12 0101+15
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 38 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.12 voice adc gain settings 0110+18 0111+21 1000+24 table 54: audio adc input ampli?er gain bits continued ia3 ia2 ia1 ia0 gain (db) ib3 ib2 ib1 ib0 table 55: voice adc input ampli?er gain register (address 21h) bit allocation bit 15 14 13 12 11 10 9 8 symbol -------- reset -------- access read and write bit 7 6 5 4 3 2 1 0 symbol - - - iv4 iv3 iv2 iv1 iv0 reset 00000000 access read and write table 56: description of voice adc input ampli?er gain register bits bit symbol description 15 to 8 - not used 7 to 5 - default 000 4 to 0 iv[4:0] voice adc input ampli?er gain. a 5-bit value to program the voice ampli?er gain in steps of 1.5 db (21 settings). default 0 0000. see t ab le 57 . table 57: voice adc input ampli?er gain bits iv4 iv3 iv2 iv1 iv0 gain (db) 000000 (default) 00001 +1.5 00010+3 00011 +4.5 00100+6 00101 +7.5 :::::: 10011 +28.5 10100+30 ::::: not used 11111 not used
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 39 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 11.13 supplemental settings 1 11.14 supplemental settings 2 table 58: supplemental settings 1 register (address 30h) bit allocation bit 15 14 13 12 11 10 9 8 symbol -------- reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol pdt------- reset 00000000 access read and write table 59: description of supplemental settings 1 register bits bit symbol description 15 to 8 - default 0000 0000 7 pdt power down time. bit pdt selects the time of the sdac power-down sequence. 1 = 1024/f s seconds 0 = 512/f s seconds (default) 6 to 0 - default 000 0000 table 60: supplemental settings 2 register (address 31h) bit allocation bit 15 14 13 12 11 10 9 8 symbol -------- reset 00000000 access read and write bit 7 6 5 4 3 2 1 0 symbol - dith2 dith1 dith0 - - vmtp pdlna reset 00000000 access read and write table 61: description of supplemental settings 2 register bits bit symbol description 15 to 7 - default 0000 0000 0 6 to 4 dith[2:0] dac dither control. a 3-bit value to control the dithering of the sdac. default 000. see t ab le 62 . 3 to 2 - default 00 1 vmtp voice mute period control. bit vmpt selects the voice adc mute period at power-up. 1 = mute for 1024 samples (1024/f s ) 0 = mute for 2048 samples (2048/f s ; default)
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 40 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 12. limiting values [1] all supply connections must be made to the same power supply. [2] esd behavior is tested in accordance with jedec ii standard: a) human body model (hbm); equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. b) machine model (mm); equivalent to discharging a 200 pf capacitor through a 0.75 m h series inductor. 13. thermal characteristics 0 pdlna power-down voice lna. bit pdlna is to power-down the voice adc lna. it should be noted that disabling the lna requires a recovery time de?ned by the external rc circuit. 1 = power-down 0 = power-on (default) table 62: dac dither control bits dith2 dith1 dith0 function 0 0 0 dc dither (mid level); default 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 dc dither (low level) 1 0 1 dc plus ac dither (low level) 1 1 0 dc dither (high level) 1 1 1 dc plus ac dither (high level) table 61: description of supplemental settings 2 register bits continued bit symbol description table 63: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage [1] - 4.0 v t xtal(max) maximum crystal temperature - 150 c t stg storage temperature - 65 +125 c t amb ambient temperature - 20 +85 c v esd electrostatic discharge voltage hbm [2] - 2000 +2000 v mm [2] - 200 +200 v table 64: thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 85 k/w
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 41 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 14. static characteristics table 65: characteristics v ddd =v dda(ad) =v dda(da) = 3.3 v; t amb =25 c; r l =22k w ; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dda(ad) adc analog supply voltage [1] 2.7 3.3 3.6 v v dda(da) dac analog supply voltage [1] 2.7 3.3 3.6 v v ddd digital supply voltage [1] 2.7 3.3 3.6 v i dda(ad) adc analog supply current f adc = 48 khz - 30 - ma f adc = 96 khz - 31 - ma i dda(da) dac analog supply current f dac = 48 khz - 20 - ma f dac = 96 khz - 32 - ma i ddd digital supply current f adc = f dac = 48 khz; f voice = 48 khz -31-ma f adc = f dac = 96 khz; f voice = 48 khz -55-ma i ddd(pd) digital supply current in power down-mode audio and voice adcs power-down -18-ma dac power-down - 14 - ma digital input pins (5 v tolerant ttl compatible) v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v ? i li ? input leakage current - - 1 m a c i input capacitance - - 10 pf digital output pins v oh high-level output voltage i oh = - 2 ma 0.85v ddd --v v ol low-level output voltage i ol = 2 ma - - 0.4 v analog-to-digital converter v ref reference voltage on pin v ref with respect to v ssa(ad) 0.45v dda(ad) 0.5v dda(ad) 0.55v dda(ad) v v adcp positive reference voltage of adc -v dda(ad) -v v adcn negative reference voltage of adc 0.0 0.0 0.0 v r o output resistance on pin v ref -5-k w r i(adc) input resistance of audio adc -10-k w
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 42 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder [1] all supply connections must be made to the same power supply unit. 15. dynamic characteristics r i(vadc) input resistance of voice adc -5-k w digital-to-analog converter r l load resistance 4 - - k w r o output resistance - 1 - k w table 65: characteristics continued v ddd =v dda(ad) =v dda(da) = 3.3 v; t amb =25 c; r l =22k w ; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. symbol parameter conditions min typ max unit table 66: characteristics v ddd = v dda(ad) = v dda(da) = 3.3 v; f i = 1 khz; t amb = 25 c; r l = 22 k w ; sampling frequency f s = 48 khz; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. symbol parameter conditions min typ max unit audio analog-to-digital converter d 0 digital output level at 0 db setting; 900 mv input [1] [2] - 2.5 - 1.2 - 0.7 db at 3 db setting; 637 mv input [2] - - 1.2 - db at 6 db setting; 451 mv input [2] - - 1.2 - db at 9 db setting; 319 mv input [2] - - 1.2 - db at 12 db setting; 226 mv input [2] - - 1.2 - db at 15 db setting; 160 mv input [2] - - 1.2 - db at 18 db setting; 113 mv input [2] - - 1.2 - db at 21 db setting; 80 mv input [2] - - 1.2 - db at 24 db setting; 57 mv input [2] - - 1.2 - db d v i input voltage unbalance between channels - 0.1 - db
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 43 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder (thd + n)/s total harmonic distortion-plus-noise to signal ratio normal mode; at - 1 dbfs at 0 db setting - - 88 - 82 db at 3 db setting - - 88 - db at 6 db setting - - 88 - db at 9 db setting - - 88 - db at 12 db setting - - 88 - db at 15 db setting - - 87 - db at 18 db setting - - 85 - db at 21 db setting - - 83 - db at 24 db setting - - 82 - db normal mode; at - 60 dbfs; a-weighted at 0 db setting - - 37 - 30 db at 3 db setting - - 37 - db at 6 db setting - - 37 - db at 9 db setting - - 37 - db at 12 db setting - - 37 - db at 15 db setting - - 37 - db at 18 db setting - - 35 - db at 21 db setting - - 32 - db at 24 db setting - - 30 - db s/n signal-to-noise ratio code = 0; a-weighted 89 98 - db a cs channel separation - 100 - db voice analog-to-digital converter v i(rms) input voltage (rms value) at 0 dbfs digital output; 2.2 k w source impedance - 50.0 - mv (thd + n)/s total harmonic distortion-plus-noise to signal ratio at - 1 dbfs - - 78 - db at - 20 dbfs - - 65 - db at - 40 dbfs; a-weighted - - 47 - db s/n signal-to-noise ratio code = 0; a-weighted - 87 - db digital-to-analog converter differential mode v o(rms) output voltage (rms value) at 0 dbfs digital input 1.9 2.0 2.1 v d v o output voltage unbalance between channels - < 0.1 - db (thd + n)/s total harmonic distortion-plus-noise to signal ratio at 0 dbfs - - 98 - 93 db at - 20 dbfs - - 90 - db at - 60 dbfs; a-weighted - - 50 - 45 db s/n signal-to-noise ratio code = 0; a-weighted 100 110 - db a cs channel separation - 114 - db table 66: characteristics continued v ddd = v dda(ad) = v dda(da) = 3.3 v; f i = 1 khz; t amb = 25 c; r l = 22 k w ; sampling frequency f s = 48 khz; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. symbol parameter conditions min typ max unit
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 44 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder [1] the input voltage can be up to 2 v (rms) when the current through the adc input pin is limited to approximately 1 ma by using a series resistor. [2] the input voltage to the adc scales proportionally with the power supply voltage. 15.1 timing single-ended mode v o(rms) output voltage (rms value) at 0 dbfs digital input - 1.0 - v d v o output voltage unbalance between channels - < 0.1 - db (thd + n)/s total harmonic distortion-plus-noise to signal ratio at 0 dbfs - - 88 - db at - 20 dbfs - - 85 - db at - 60 dbfs; a-weighted - - 45 - db s/n signal-to-noise ratio code = 0; a-weighted - 105 - db a cs channel separation - 110 - db table 66: characteristics continued v ddd = v dda(ad) = v dda(da) = 3.3 v; f i = 1 khz; t amb = 25 c; r l = 22 k w ; sampling frequency f s = 48 khz; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. symbol parameter conditions min typ max unit table 67: timing v ddd = v dda(ad) = v dda(ad) = 2.7 v to 3.6 v; t amb = - 20 c to +85 c; typical timing speci?ed at sampling frequency f s = 48 khz; unless otherwise speci?ed. symbol parameter conditions min typ max unit system clock (see figure 16 ) t sys system clock cycle time f sys = 256f s [1] 35 81 780 ns f sys = 384f s [1] 23 54 520 ns f sys = 512f s [1] 17 41 390 ns f sys = 768f s [1] 17 27 260 ns t cwl system clock low time f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns t cwh system clock high time f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns i 2 s-bus interface serial data of audio adc and dac (see figure 17 ) f bck audio bit clock frequency [2] - - 12.8 mhz t cy(bck) bck cycle time - - 78 ns t bckh bit clock high time 30 - - ns t bckl bit clock low time 30 - - ns t r rise time - - 20 ns t f fall time - - 20 ns t su(ws) word select set-up time 10 - - ns t h(ws) word select hold time 10 - - ns t su(datai) data input set-up time 10 - - ns t h(datai) data input hold time 10 - - ns t h(datao) data output hold time 0 - - ns
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 45 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder t d(datao-bck) data output to bit clock delay - - 30 ns t d(datao-ws) data output to word select delay - - 30 ns serial data of voice adc f bckv voice bit clock frequency [2] - - 6.4 mhz t cy(bckv) bckv cycle time - - 156 ns t bckvh bit clock high time 50 - - ns t bckvl bit clock low time 50 - - ns t r rise time - - 20 ns t f fall time - - 20 ns t su(wsv) word select set-up time 10 - - ns t h(wsv) word select hold time 10 - - ns t h(datav) data output hold time 0 - - ns t d(datav-bckv) data output to bit clock delay - - 30 ns t d(datav-wsv) data output to word select delay - - 30 ns t d(wsv-bckv) word select to bit clock delay wsv-out mode - 30 - +30 ns l3-bus interface (see figure 18 and figure 19 ) l3clock timing f cy(clk)l3 l3clock frequency - - 2000 khz t cy(clk)l3 l3clock cycle time 500 - - ns t clk(l3)h l3clock high time 250 - - ns t clk(l3)l l3clock low time 250 - - ns l3mode timing t su(l3)a l3mode set-up time in address mode 190 - - ns t h(l3)a l3mode hold time in address mode 190 - - ns t su(l3)d l3mode set-up time in data transfer mode 190 - - ns t h(l3)d l3mode hold time in data transfer mode 190 - - ns t stp(l3) l3mode stop time in data transfer mode 190 - - ns l3data timing t su(l3)da l3data set-up time in data transfer and address mode 190 - - ns t h(l3)da l3data hold time in data transfer and address mode 30--ns t d(l3)r l3data delay time for read data 0 - 50 ns table 67: timing continued v ddd = v dda(ad) = v dda(ad) = 2.7 v to 3.6 v; t amb = - 20 c to +85 c; typical timing speci?ed at sampling frequency f s = 48 khz; unless otherwise speci?ed. symbol parameter conditions min typ max unit
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 46 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder [1] the system clock should not exceed 58 mhz in any mode. [2] the bit clock frequency should not exceed 256 times the corresponding sampling frequency. [3] c b is the total capacitance for each bus line. [4] to be suppressed by the input ?lter. t dis(l3)r l3data disable time for read data 0 - 50 ns i 2 c-bus interface timing (see figure 20 ) scl timing f scl scl clock frequency 0 - 400 khz t low scl low time 1.3 - - m s t high scl high time 0.6 - - m s t r rise time sda and scl [3] 20 + 0.1c b - 300 ns t f fall time sda and scl [3] 20 + 0.1c b - 300 ns sda timing t buf bus free time between stop and start condition 1.3 - - m s t su;sta set-up time repeated start 0.6 - - m s t hd;sta hold time start condition 0.6 - - m s t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - m s t su;sto set-up time stop condition 0.6 - - m s t sp pulse width of spikes [4] 0 - 50 ns c b capacitive load for each bus line - - 400 pf table 67: timing continued v ddd = v dda(ad) = v dda(ad) = 2.7 v to 3.6 v; t amb = - 20 c to +85 c; typical timing speci?ed at sampling frequency f s = 48 khz; unless otherwise speci?ed. symbol parameter conditions min typ max unit fig 16. system clock timing mgr984 t sys t cwh t cwl
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 47 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder fig 17. i 2 s-bus serial interface timing mgs756 ws bck datao datai t f t r t h(ws) t su(ws) t bckh t bckl t cy(bck) t h(datao) t su(datai) t h(datai) t d(datao-bck) t d(datao-ws) fig 18. l3-bus address mode timing t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 48 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 16. test information 16.1 quality information the general quality speci?cation for integrated circuits, snw-fq-611 is applicable. fig 19. l3-bus data transfer (write and read) mode timing t stp(l3) t su(l3)d t h(l3)da t en(l3)r t h(l3)r t su(l3)da t h(l3)d t cy(clk)l3 bit 0 l3mode l3clock l3data read l3data write bit 7 mgu015 t clk(l3)h t clk(l3)l t su(l3)r t dis(l3)r fig 20. i 2 c-bus timing msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 49 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 17. package outline fig 21. package outline sot307-2 (qfp44) unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 97-08-01 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.1
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 50 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 18. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 19. soldering 19.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 19.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 19.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results:
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 51 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 19.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 19.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. table 68: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 52 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages.
9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 53 of 55 philips semiconductors UDA1384 multichannel audio coder-decoder 20. revision history table 69: revision history document id release date data sheet status change notice doc. number supersedes UDA1384_2 20050117 product data sheet - 9397 750 14366 UDA1384_1 modi?cations: ? the format of this data sheet has been redesigned to comply with the new presentation and information standard of philips semiconductors ? section 4 quic k ref erence data : added values for i ddd(pd) ? section 14 static char acter istics : added values for i ddd(pd) ? section 15 dynamic char acter istics : removed psrr speci?cation and (thd+n)/s at - 20 dbfs, added (thd+n)/s for dac differential mode UDA1384_1 20031009 preliminary speci?cation - 9397 750 12043 -
philips semiconductors UDA1384 multichannel audio coder-decoder 9397 750 14366 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 17 january 2005 54 of 55 21. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 22. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 23. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 24. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 17 january 2005 document number: 9397 750 14366 published in the netherlands philips semiconductors UDA1384 multichannel audio coder-decoder 25. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 multiple format data interface . . . . . . . . . . . . . . 2 2.3 digital sound processing. . . . . . . . . . . . . . . . . . 2 2.4 advanced audio con?guration . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 7 8.1 system clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 audio analog-to-digital converter (audio adc) . 8 8.3 voice analog-to-digital converter (voice adc) 8 8.4 decimation ?lter of audio adc . . . . . . . . . . . . . 8 8.5 decimation ?lter of voice adc . . . . . . . . . . . . . 8 8.6 interpolation ?lter of dac . . . . . . . . . . . . . . . . . 9 8.7 noise shaper of dac . . . . . . . . . . . . . . . . . . . . 9 8.8 digital mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.9 audio digital-to-analog converters . . . . . . . . . 10 8.10 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10 8.11 audio digital interface . . . . . . . . . . . . . . . . . . . 11 8.12 voice digital interface . . . . . . . . . . . . . . . . . . . 14 8.13 dsd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.14 microcontroller interface mode . . . . . . . . . . . . 15 9 l3-bus interface . . . . . . . . . . . . . . . . . . . . . . . . 15 9.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.2 device addressing . . . . . . . . . . . . . . . . . . . . . 16 9.3 register addressing . . . . . . . . . . . . . . . . . . . . 16 9.4 data write mode . . . . . . . . . . . . . . . . . . . . . . . 18 9.5 data read mode . . . . . . . . . . . . . . . . . . . . . . . 18 10 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 19 10.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.2 characteristics of the i 2 c-bus . . . . . . . . . . . . . 19 10.3 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.4 byte transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.5 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.6 start and stop conditions . . . . . . . . . . . . . . . . 20 10.7 acknowledgment . . . . . . . . . . . . . . . . . . . . . . 20 10.8 device address . . . . . . . . . . . . . . . . . . . . . . . . 21 10.9 register address. . . . . . . . . . . . . . . . . . . . . . . 21 10.10 write and read data . . . . . . . . . . . . . . . . . . . . 21 10.11 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.12 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 register mapping . . . . . . . . . . . . . . . . . . . . . . 23 11.1 address mapping . . . . . . . . . . . . . . . . . . . . . . 23 11.2 register mapping . . . . . . . . . . . . . . . . . . . . . . 25 11.3 system settings . . . . . . . . . . . . . . . . . . . . . . . 27 11.4 audio adc and dac subsystem settings. . . . 29 11.5 voice adc system settings . . . . . . . . . . . . . . 30 11.6 status output register . . . . . . . . . . . . . . . . . . . 32 11.7 dac channel selection . . . . . . . . . . . . . . . . . . 33 11.8 dac features settings. . . . . . . . . . . . . . . . . . . 34 11.9 dac channel 1 to channel 6 settings . . . . . . . 36 11.10 dac mixing channel settings . . . . . . . . . . . . . 36 11.11 audio adc 1 and adc 2 input ampli?er gain settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.12 voice adc gain settings. . . . . . . . . . . . . . . . . 38 11.13 supplemental settings 1. . . . . . . . . . . . . . . . . 39 11.14 supplemental settings 2. . . . . . . . . . . . . . . . . 39 12 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 40 13 thermal characteristics . . . . . . . . . . . . . . . . . 40 14 static characteristics . . . . . . . . . . . . . . . . . . . 41 15 dynamic characteristics . . . . . . . . . . . . . . . . . 42 15.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 16 test information. . . . . . . . . . . . . . . . . . . . . . . . 48 16.1 quality information . . . . . . . . . . . . . . . . . . . . . 48 17 package outline . . . . . . . . . . . . . . . . . . . . . . . . 49 18 handling information . . . . . . . . . . . . . . . . . . . 50 19 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 19.1 introduction to soldering surface mount packages 50 19.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 50 19.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 50 19.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 51 19.5 package related soldering information . . . . . . 51 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 53 21 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 54 22 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 23 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 24 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 25 contact information . . . . . . . . . . . . . . . . . . . . 54

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